发明名称 EARLY DESIGN CYCLE OPTIMZATION
摘要 Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
申请公布号 US2014101629(A1) 申请公布日期 2014.04.10
申请号 US201314100553 申请日期 2013.12.09
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALPERT CHARLES JAY;AVERILL, III ROBERT M.;LI ZHUO;NEVES JOSE L. P.;QUAY STEPHEN T.
分类号 G06F17/50 主分类号 G06F17/50
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