发明名称 |
Interpolative divider linearity enhancement techniques |
摘要 |
A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal. |
申请公布号 |
US8692599(B2) |
申请公布日期 |
2014.04.08 |
申请号 |
US201213592160 |
申请日期 |
2012.08.22 |
申请人 |
GONG XUE-MEI;ELDREDGE ADAM B.;HARA SUSUMU;SILICON LABORATORIES INC. |
发明人 |
GONG XUE-MEI;ELDREDGE ADAM B.;HARA SUSUMU |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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