发明名称 Digital phase locked loop
摘要 An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal. The digitally controlled oscillator circuitry further comprises adjustment circuitry capable of applying a phase adjustment to the clock signal in response to a second digital control word.
申请公布号 US8692598(B2) 申请公布日期 2014.04.08
申请号 US201213403358 申请日期 2012.02.23
申请人 HAVENS JOSEPH H.;LSI CORPORATION 发明人 HAVENS JOSEPH H.
分类号 H03L7/06 主分类号 H03L7/06
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