发明名称 Method and device for loading and executing instructions with deterministic cycles in a multicore avionic system having a bus of which the access time is not predictable
摘要 A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.
申请公布号 US8694747(B2) 申请公布日期 2014.04.08
申请号 US201013376022 申请日期 2010.06.02
申请人 JEGU VICTOR;TRIQUET BENOIT;ASPRO FREDERIC;BONIOL FREDERIC;PAGETTI CLAIRE;AIRBUS OPERATIONS S.A.S. 发明人 JEGU VICTOR;TRIQUET BENOIT;ASPRO FREDERIC;BONIOL FREDERIC;PAGETTI CLAIRE
分类号 G06F13/10 主分类号 G06F13/10
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