发明名称 MICROCOMPUTER AND INSTRUCTION PROCESSING METHOD IN MICROCOMPUTER
摘要 PROBLEM TO BE SOLVED: To prevent an occurrence of a branch penalty in a microcomputer.SOLUTION: The microcomputer includes a branch detection circuit for detecting a branch instruction from an instruction outputted from an instruction memory to an instruction queue, a branch destination determination circuit for determining whether a corresponding branch instruction is stored in the instruction queue when the branch instruction is detected, and a queue control circuit. A copy object includes the range from a branch destination instruction corresponding to the detected branch instruction till the preceding instruction of the detected branch instruction. The queue control circuit stores an instruction of the copy object in the instruction queue again each time the instruction is executed. In the case that a branch condition about the branch instruction is established, the queue control circuit moves the copy object stored in the instruction queue to the head of the instruction queue.
申请公布号 JP2014059665(A) 申请公布日期 2014.04.03
申请号 JP20120203574 申请日期 2012.09.14
申请人 RENESAS ELECTRONICS CORP 发明人 FUJIOKA YUJI;YAMAZOE KIMINARI;KITAHARA TAKASHI
分类号 G06F9/38 主分类号 G06F9/38
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