发明名称 |
Providing timing-closed FinFET designs from planar designs |
摘要 |
An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase. |
申请公布号 |
US8689154(B2) |
申请公布日期 |
2014.04.01 |
申请号 |
US201213446418 |
申请日期 |
2012.04.13 |
申请人 |
RASHED MAHBUB;DOMAN DAVID;SOMASEKHAR DINESH;WANG YAN;DENG YUNFEI;JAIN NAVNEET;KYE JONGWOOK;KESHAVARZI ALI;KENGERI SUBRAMANI;VENKATESAN SURESH;GLOBALFOUNDRIES INC. |
发明人 |
RASHED MAHBUB;DOMAN DAVID;SOMASEKHAR DINESH;WANG YAN;DENG YUNFEI;JAIN NAVNEET;KYE JONGWOOK;KESHAVARZI ALI;KENGERI SUBRAMANI;VENKATESAN SURESH |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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