| 摘要 |
<p>The device has an independent core (16), a processor (26), a memory (28), and a common memory (22) that is accessible by the core. The core is arranged in a node (40) for processing of a set of tasks. A determination unit (47) is arranged to determine next task or sub-tasks. An allowance unit (48) is arranged to allow next task or sub-task to be carried out with slave cores (16E) determined according to indicators of a state of a register (42) of slave cores. Each task or sub-task is associated with an allowance condition. Independent claims are also included for the following: (1) a data processing method (2) an automatic table of events generation method.</p> |
