| 摘要 |
A processor includes a cache write queue configured to store write requests, based on store instructions directed to a cache memory issued by an instruction issuing unit, into entries provided with stream_wait flag, and to output a write request including no stream_wait flag set thereon, from among the stored write requests, to a pipeline operating unit which performs pipeline operation with respect to the cache memory, the cache write queue being further configured to determine, when a stream flag attached to the store instruction is set, that there will be succeeding store instruction directed to a data area same as that accessed by the store instruction, to set the stream_wait flag so as to store the write request into the entry, to merge the write requests based on the store instructions, directed to the same data area, into a single write request, and then to hold the merged write request. |
