发明名称 METHOD AND APPARATUS FOR VERIFYING SYSTEM ON CHIP MODEL
摘要 A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.
申请公布号 KR101375171(B1) 申请公布日期 2014.03.18
申请号 KR20060139212 申请日期 2006.12.30
申请人 发明人
分类号 G06F9/455;G06F11/28;G06F11/36 主分类号 G06F9/455
代理机构 代理人
主权项
地址