Logic gate e.g. NAND-type logic gate, for manufacturing part of locally constricted FET in digital electronic industry, has grid whose portion is positioned relative to zones so as to have field effect when channel is traversed by current

摘要

The gate e.g. NAND-type logic gate (PL1), has an elongated conducting channel (CC) exhibiting a thickness of 20 nanometer and locally comprising constriction zones (Z1, Z2) with a thickness of equal to or lower than 5 nanometer, where the gate comprises two metal grids (G1, G2). A dielectric insulation coating covers the constriction zones. A portion of one of the metal grids is positioned relative to the constriction zones so as to have field effect when the conducting channel is traversed by a current, where a length of the conducting channel is 100 nanometer. The conducting channel is designed as a nano-wire or a nano-tape. An independent claim is also included for a method for manufacturing a logic gate.