| 摘要 |
The address array circuit according to an embodiment of the present invention includes: a sorting unit which uses a clock, latches and outputs N address signals of serial input (N is a natural number greater than or equivalent to 2) in parallel in response to a plurality of commands, and outputs P test address signals (P uses a natural number greater than 1 and less than N); and an output unit which outputs the P test address signals among the N address signals to be used in response to a test mode signal. [Reference numerals] (110) Buffer; (120) Sorting unit; (121) First latch unit; (122) Second latch unit; (130) Output unit |
