| 摘要 |
An SRAM cell includes six four-terminal double gate FETs formed on four semiconductor thin film plates, in which first and third FETs, fourth and fifth FETs, third and fourth FETs, and second and sixth FETs neighbor each other and logic signal input gates thereof are formed on facing side surfaces of respective semiconductor thin film plates; the second and sixth FETs sandwich second and third plates; the threshold voltage control gates of the second, third, fourth, and sixth FETs are connected in common to a first bias wiring; threshold voltage control gates of the first and fifth FETs are connected in common to a second bias wiring; and the word line and the first and second bias wirings are arranged in a direction perpendicular to the alignment direction of the first to the fourth plates. |
