发明名称 FPGA configuration data scrambling using input multiplexers
摘要 Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.
申请公布号 US8650409(B1) 申请公布日期 2014.02.11
申请号 US20040942151 申请日期 2004.09.15
申请人 REESE DIRK;WHITE THOMAS H.;ALTERA CORPORATION 发明人 REESE DIRK;WHITE THOMAS H.
分类号 G06F21/00 主分类号 G06F21/00
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