| 摘要 |
<p>The present technology is provided to inactivate a buffer during refresh while supporting various buffer operations and to reduce current consumption of a memory, a memory according to the present invention comprising: a cell array including a plurality of word lines; a first buffer receiving a clock enable signal; a plurality of second buffers receiving commands; a refresh control unit for enabling the plurality of word lines to be sequentially activated when performing a refresh operation in a self refresh mode; a command decoder for enabling the refresh control unit to enter into the self refresh mode or escape from the self refresh mode by decoding the clock enable signal received by the first buffer and the command received by the plurality of second buffers; and a buffer control unit for inactivating the plurality of second buffers if the clock enable signal received by the first buffer is inactivated, and activating the plurality of second buffers when the refresh control unit escapes from the self refresh mode. [Reference numerals] (220) Command decoder; (230) Refresh control unit; (240) Buffer control unit; (250) Low control unit</p> |
