| 摘要 |
PROBLEM TO BE SOLVED: To obtain a RAM memory cell with which power consumption is reduced and which is useful for memory structure having very long work length. SOLUTION: This RAM memory cell comprises first and second cross- connected CMOS inverters 12, 13 comprising respectively PMOS pull-up transistors M3, M4 and NMOS pull-down transistors M1, M2, and first and second success transistors M5, M6 connecting respectively the second inverter 13 and the first inverter 12 to corresponding bit lines. And source temporal of the pull-down transistors M1, M2 are connected to pre-charge lines PL extending in parallel to respective word lines. Further, the first and the second access transistors M5, M6 are PMOS transistors whose gate terminals are connected to word lines WL.
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