发明名称 Netlist partitioning for characterizing effect of within-die variations
摘要 Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.
申请公布号 US8612199(B2) 申请公布日期 2013.12.17
申请号 US20070961787 申请日期 2007.12.20
申请人 SHRIVASTAVA SACHIN;PARAMESWARAN HARINDRANATH;CADENCE DESIGN SYSTEMS, INC. 发明人 SHRIVASTAVA SACHIN;PARAMESWARAN HARINDRANATH
分类号 G06F17/50 主分类号 G06F17/50
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