| 摘要 |
In the present invention, the voltage Edc of a detection subject is divided and detected by means of a voltage-dividing circuit (30) wherein multiple resistance circuits (31), each of which is formed by parallel-connecting multiple resistors, are connected in series. The output from multiple voltage detection circuits, which are formed for example from an op-amp (38) connected to any three locations in the voltage-dividing circuit (30) (with one of the locations being connected through a switch (SW35)), is input to a CPU (37) twice, that is when the switch (SW35) turns on and when the switch turns off. On the basis of these two voltage measurements, the CPU (37) determines that some kind of fault has occurred when there is a fault such as a short circuit/disconnection of the resistors in the resistance circuits (31) associated with the aforementioned three connected locations in the voltage-dividing circuit (30). |
