发明名称 EDGE CONNECT WAFER LEVEL STACKING
摘要 A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.
申请公布号 US2013330905(A1) 申请公布日期 2013.12.12
申请号 US201313970028 申请日期 2013.08.19
申请人 TESSERA, INC. 发明人 HABA BELGACEM;OGANESIAN VAGE
分类号 H01L21/306 主分类号 H01L21/306
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