Variability resilient sense amplifier with reduced energy consumption

摘要

Disclosed is a method for improving writability of an SRAM cell, by applying a first voltage (VSS+”v1) higher than the global ground voltage (VSS) and a third voltage (VDD+”v3) higher the global supply voltage (VDD) to the ground resp supply nodes of the invertors of the SRAM cell, and by pre-charging one of the complementary bitlines (WBL, WBL/) to the global ground voltage (VSS), and by applying a second voltage (VDD+”v2) higher than the global supply voltage (VDD) to the access transistors (Mpl, Mpr) during a write operation to the SRAM cell.