发明名称 PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR IMPROVING THICKNESS UNIFORMITY OF THE SEMICONDUCTOR LAYER
摘要 <p>The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate (1), a dielectric layer (2) and a semiconductor layer (3) having a thickness of less than or equal to 100 nm, said semiconductor layer (3) being covered with a sacrificial oxide layer (4), comprising: measuring, at a plurality of points distributed over the surface of the, structure, the thickness of the sacrificial oxide layer (4) and of the semiconductor layer (3), so as to produce a mapping of the thickness of the semiconductor layer (3) and to determine, from said measurements, the average thickness of the semiconductor layer (3), selective etching of the sacrificial oxide layer (4) so as to expose the semiconductor layer (3), and carrying out a chemical etching of the semiconductor layer (3), the application, temperature and/or duration conditions of which are adjusted as a function of said mapping and/or of the mean thickness of the semiconductor layer (3), so as to thin, at least locally, said semiconductor layer (3) by a thickness identified as being an overthickness at the end of the measurement step.</p>
申请公布号 WO2013175278(A1) 申请公布日期 2013.11.28
申请号 WO2013IB00857 申请日期 2013.05.01
申请人 SOITEC 发明人 SCHWARZENBACH, WALTER;DURET, CARINE;BOEDT, FRANCOIS
分类号 H01L21/66 主分类号 H01L21/66
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