| 摘要 |
PURPOSE: To prevent the overhead of a vector processor which encounters an exception by blocking a vector instruction so as not to be supplied to a vector processing means in response to an exception state and keeping supplying an instruction to a scalar processing means. CONSTITUTION: A scalar processor is provided with the vector processor 30 and the vector processor 30 is provided with exception logic circuits 72 and 82. An instruction decoder 65 is connected to a controller 60 and the controller 60 prevents the vector instruction from being supplied to the vector processor 30 when the vector processor 30 is diabled by the occurrence of an arithmetic exception. The scalar processor continues the execution of a scalar instruction regardless of the occurrence of an the arithmetic exception in the vector processor 30. Thus, faults generated in a data processing system when the vector processor encounters the arithmetic exception are minimized. |
