发明名称 DELAY COMPENSATION CIRCUIT
摘要 A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.
申请公布号 US2013285734(A1) 申请公布日期 2013.10.31
申请号 US201213458205 申请日期 2012.04.27
申请人 NASCIMENTO IVAN CARLOS RIBEIRO;VILAS BOAS ANDRE LUIS;FREESCALE SEMICONDUCTOR, INC. 发明人 NASCIMENTO IVAN CARLOS RIBEIRO;VILAS BOAS ANDRE LUIS
分类号 H03K17/00 主分类号 H03K17/00
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