| 摘要 |
The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data.
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