Multi-rate sampling for network receiving nodes using distributed clock synchronization

摘要

Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a first clock having a first clock frequency (f1) with a first clock frequency tolerance (Deltaf1), and a second timing engine that samples bits received by the receiver with a second clock having a second clock frequency (f2) with a second clock frequency tolerance (Deltaf2). The second clock frequency is less than the first clock frequency. The network receiver may also include a third timing engine that samples bits received by the receiver with a third clock having a third clock frequency (f3) with a third clock frequency tolerance (Deltaf3). The third clock frequency may be greater than the first clock frequency. The network receiver may also include a timing engine resolver that determines which of the first, second, and third timing engines correctly samples the bits received by the receiver; wherein f1-Deltaf1