发明名称 INFORMATION PROCESSING APPARATUS, PROCESSOR, AND PREFETCH METHOD
摘要 PROBLEM TO BE SOLVED: To provide an information processing apparatus in which accuracy of prefetch is enhanced while suppressing excessive generation/execution of a prefetch instruction.SOLUTION: An information processing apparatus 9 includes: a main memory 90; a cache memory 91; an instruction generation part 92 for generating a plurality of instructions regarding access to the main memory 90, containing a load instruction for loading data stored in the main memory 90; an instruction control part 93 for determining an execution order of instructions generated by the instruction generation part 92 to output the instructions in the determined execution order; and an order execution part 94 for executing an instruction output from the instruction control part 93. The instruction control part 93 generates, when it is determined that a load instruction cannot overtake a previously generated instruction, a prefetch instruction for data to be loaded by the load instruction to output it. The instruction execution part 94 prefetches, on the basis of the prefetch instruction output from the instruction control part 93, data stored in the main memory to a cache memory.
申请公布号 JP2013210955(A) 申请公布日期 2013.10.10
申请号 JP20120082204 申请日期 2012.03.30
申请人 NEC CORP 发明人 NAKAGAWA KOICHI
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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