发明名称 |
HIGH SPEED DUTY CYCLE CORRECTION AND DOUBLE TO SINGLE ENDED CONVERSION CIRCUIT FOR PLL |
摘要 |
The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.
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申请公布号 |
US2013257499(A1) |
申请公布日期 |
2013.10.03 |
申请号 |
US201113522745 |
申请日期 |
2011.08.23 |
申请人 |
WANG YOUHUA;ZHANG JUNAN;FU DONGBING;HU GANGYI;LIU JUN;LI RUZHANG;CHEN GUANGBING;CHINA ELECTRONIC TECHNOLOGY CORPORATION |
发明人 |
WANG YOUHUA;ZHANG JUNAN;FU DONGBING;HU GANGYI;LIU JUN;LI RUZHANG;CHEN GUANGBING |
分类号 |
H03K5/06 |
主分类号 |
H03K5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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