| 摘要 |
This invention addresses the problem of making it possible to guarantee the clock cycle under worst-case performance without degrading transfer throughput. A bus access arbiter (300) is provided with an access mode judgment part (100) and a round-robin arbitration part (200). When bus access is generated from a plurality of masters (M0, M1), the access mode judgment part (100) determines whether the access mode of the connected masters is a sequential access mode or a single access mode. The round-robin arbitration part (200) dynamically switches the access arbitration scheme for arbitrating bus access in accordance with the access mode. The access mode judgment part (100) is provided with an access interval counter (10), a sequential access counter (20), and an access mode state register (40) for storing the determined access mode state for each master, and updates the access mode state on the basis of the access interval and the number of sequential accesses. |
