| 摘要 |
In a computer comprising multiple processing elements and suitable for executing the software implementation of a UML activity diagram, nodes or primitives that connect activities within the diagram are implemented by a sequencing arrangement comprising detecting that event signals necessary to trigger the node have been received, and either instructing a processor to perform the activity that follows from the node, or dispatching a further event signal to another node. The sequencer comprises detecting elements that are triggered by receiving a event signal corresponding to an element of the activity diagram. The arrangement may comprise a barrier-counter element (BCE), where the barrier 112 breaks after receiving the required number of event signals, which triggers the dispatch of instructions 114. The event signal may be a pulse issued by a timer within the computer. In a specific embodiment the BCEs in the sequencing arrangement are arranged in disjoint groups of detection elements, each responsible for the performance of a separate task. |
