发明名称 Area efficient arrangement of interface devices within an integrated circuit
摘要 An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
申请公布号 US8549257(B2) 申请公布日期 2013.10.01
申请号 US20110929236 申请日期 2011.01.10
申请人 MISHRA VIKAS;WANG BINGDA BRANDON;ARM LIMITED 发明人 MISHRA VIKAS;WANG BINGDA BRANDON
分类号 G06F15/00;G06F9/06 主分类号 G06F15/00
代理机构 代理人
主权项
地址