发明名称 SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SAME
摘要 In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.
申请公布号 US2013241042(A1) 申请公布日期 2013.09.19
申请号 US201113879911 申请日期 2011.09.28
申请人 KWON YONG-TAE;NEPES CORPORATION 发明人 KWON YONG-TAE
分类号 H01L23/00 主分类号 H01L23/00
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