发明名称 Embedded system capable of decreasing interrupt frequency of arm processor thereof
摘要 An embedded system includes an ARM processor and a number of b-bit peripheral processors connected to the ARM processor through a converting chip. The ARM processor includes pins P0~Pa-1 divided into teams T1~TN, each of which includes b pins, a and b are integral multiple of 8, wherein a=N×b. The number of the peripheral processors is N and each team corresponds to one peripheral processor. The converting chip reads an a-bit data from the ARM processor, converts the data into a plurality of b-bit data, and transfers each b-bit data to a peripheral processor, where the number of the b-bit data is N. The converting chip further reads one b-bit data from each peripheral processor in sequence, converts the read plurality of b-bit data into an a-bit data, and transfers the a-bit data to the ARM processor.
申请公布号 US8539133(B2) 申请公布日期 2013.09.17
申请号 US201113189581 申请日期 2011.07.25
申请人 HUANG REN-WEN;FU TAI HUA INDUSTRY (SHENZHEN) CO., LTD.;HON HAI PRECISION INDUSTRY CO., LTD. 发明人 HUANG REN-WEN
分类号 G06F13/38;G06F13/40 主分类号 G06F13/38
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