发明名称 |
Parity-check-code decoder and receiving system |
摘要 |
A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.
|
申请公布号 |
US8527857(B2) |
申请公布日期 |
2013.09.03 |
申请号 |
US20090613059 |
申请日期 |
2009.11.05 |
申请人 |
WANG CHENG-KANG;LIN HOU-WEI;HUNG CHIA-CHUN;REALTEK SEMICONDUCTUR CORP. |
发明人 |
WANG CHENG-KANG;LIN HOU-WEI;HUNG CHIA-CHUN |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|