发明名称
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock and data recovery circuit and a recovery method, and a station-side apparatus employing the recovery circuit, capable of preventing occurrence of a phenomenon that, when entering a no-signal interval between burst signals, a frequency is temporarily deviated from that of a reference clock signal considerably. <P>SOLUTION: In the clock and data recovery circuit 10, including a recovery clock signal initializing means 10B for generating a recovery clock signal so that the frequency of a divided-frequency clock signal, obtained by dividing frequency of the recovery clock signal, becomes closer to that of a reference clock signal, when entering a no signal interval; a frequency divider 16 resets a current count value indicating a phase of the divided-frequency clock signal to a predetermined value, before the recovery clock signal initializing means 10B operates, and resumes counting with the timing of phase synchronization with the reference clock signal. Thus, phase synchronization is attained, prior to initialization of the frequency of the recovery clock signal. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP5267301(B2) 申请公布日期 2013.08.21
申请号 JP20090099704 申请日期 2009.04.16
申请人 发明人
分类号 H04L7/033 主分类号 H04L7/033
代理机构 代理人
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