发明名称 Processing of multiple cells in a network device with two reads and two writes on one clock cycle
摘要 A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.
申请公布号 US8514875(B2) 申请公布日期 2013.08.20
申请号 US20060594743 申请日期 2006.11.09
申请人 WU CHIEN-HSIEN;CHEOK YOOK-KHAI;OPSASNICK EUGENE;BROADCOM CORPORATION 发明人 WU CHIEN-HSIEN;CHEOK YOOK-KHAI;OPSASNICK EUGENE
分类号 G06F13/00;G06F12/08;G06F13/16;G06F13/28;G11C7/10 主分类号 G06F13/00
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