BUFFER MANAGEMENT FOR GRAPHICS PARALLEL PROCESSING UNIT

摘要

The techniques are generally related to a method of executing graphics data processing operations in parallel and also in a pipeline fashion. A first thread is executed on a first unit (28A) of e.g. a shader processor of a GPU (26) and a second thread is executed in parallel on a second unit (28N). The data produced by the execution of the first thread is then consumed by the second unit executing the second thread. A management unit (18) within an IC (16) that includes the GPU receives a request from the first unit to store the data produced thereby into a buffer (22A-22N) in a global memory external to the IC, the buffer comprising a FIFO buffer, an example thereof being a ring buffer, and determines a location where the data produced by the execution of the first thread is to be stored. Upon receiving a request from the second unit to retrieve said data produced by execution of the first thread, the management unit determines whether the data of the first thread is available for retrieval for consumption by the second thread.