发明名称 Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory
摘要 In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.
申请公布号 US2013176790(A1) 申请公布日期 2013.07.11
申请号 US201213570826 申请日期 2012.08.09
申请人 NGUYEN HAO THAI;LEE JUAN CARLOS;LEE SEUNGPIL;PARK JUNGMIN;MUI MAN LUNG 发明人 NGUYEN HAO THAI;LEE JUAN CARLOS;LEE SEUNGPIL;PARK JUNGMIN;MUI MAN LUNG
分类号 G11C16/10 主分类号 G11C16/10
代理机构 代理人
主权项
地址