发明名称 |
NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION |
摘要 |
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
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申请公布号 |
US2013171785(A1) |
申请公布日期 |
2013.07.04 |
申请号 |
US201213343331 |
申请日期 |
2012.01.04 |
申请人 |
SHROFF MEHUL D.;HALL MARK D. |
发明人 |
SHROFF MEHUL D.;HALL MARK D. |
分类号 |
H01L21/8239 |
主分类号 |
H01L21/8239 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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