发明名称 MACHINE CHECK SUMMARY REGISTER
摘要 <p>In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.</p>
申请公布号 WO2013101111(A1) 申请公布日期 2013.07.04
申请号 WO2011US67935 申请日期 2011.12.29
申请人 INTEL CORPORATION;VARGAS, JOSE (ANDY), A.;KUMAR, MOHAN, J.;CROSSLAND, JAMES, B.;NACHIMUTHU, MURUGASAMY (SAMMY), K.;YIGZAW, THEODROS (THEO) 发明人 VARGAS, JOSE (ANDY), A.;KUMAR, MOHAN, J.;CROSSLAND, JAMES, B.;NACHIMUTHU, MURUGASAMY (SAMMY), K.;YIGZAW, THEODROS (THEO)
分类号 G06F11/22;G06F11/08;G06F15/80 主分类号 G06F11/22
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