CIRCUIT FOR ENHANCING ROBUSTNESS OF SUB-THRESHOLD SRAM MEMORY CELL

摘要

Disclosed is a circuit for enhancing the robustness of a sub-threshold SRAM memory cell. The circuit functions as an auxiliary circuit of the sub-threshold SRAM memory cell, and the output of the circuit is connected to a PMOS transistor in the sub-threshold SRAM memory cell and the substrate of the PMOS transistor within the circuit. The circuit comprises a PMOS transistor threshold voltage detection circuit in the SRAM memory cell and an amplifier having a differential input and a single-ended output. By means of voltage fluctuations of PMOS transistor and NMOS transistor, thresholds induced by a detection technique, the voltage of the PMOS transistor in the sub-threshold SRAM memory cell and of the substrate of the PMOS substrate in the circuit are self-adaptively changed, thereby adjusting the threshold voltage and matching the threshold voltage of the PMOS with the threshold voltage of the NMOS. Noise margin of the sub-threshold SRAM memory cell is thus enhanced, and the robustness of said memory cell is also effectively enhanced.