发明名称 Solder bump confinement system for an integrated circuit package
摘要 A solder bump confinement system is provided includes a substrate; a contact material patterned on the substrate; an inner passivation layer deposited over the contact material and the substrate; an under bump material pad over the contact material; an under bump material defining layer, having a bump opening contained therein, directly on the under bump material pad in which the under bump material defining layer has a thickness in the range of 200 Angstrom to 1500 Angstrom; and a system interconnect formed over the contact material and coupled to the under bump material defining layer and the under bump material pad through the bump opening.
申请公布号 US8466557(B2) 申请公布日期 2013.06.18
申请号 US20100756067 申请日期 2010.04.07
申请人 LIN YAOJIAN;MARIMUTHU PANDI CHELVAM;PENDSE RAJENDRA D.;STATS CHIPPAC LTD. 发明人 LIN YAOJIAN;MARIMUTHU PANDI CHELVAM;PENDSE RAJENDRA D.
分类号 H01L23/48 主分类号 H01L23/48
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