| 发明名称 |
Method of plating through wafer vias in a wafer for 3D packaging |
| 摘要 |
A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.
|
| 申请公布号 |
US8455357(B2) |
申请公布日期 |
2013.06.04 |
| 申请号 |
US200913120988 |
申请日期 |
2009.09.28 |
| 申请人 |
BESLING WILLEM FREDERIK ADRIANUS;ROOZEBOOM FREDDY;LAMY YANN PIERRE ROGER;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
BESLING WILLEM FREDERIK ADRIANUS;ROOZEBOOM FREDDY;LAMY YANN PIERRE ROGER |
| 分类号 |
H01L21/44;H01L21/311;H01L21/4763;H01L23/053;H01L23/12;H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L21/44 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
