发明名称 |
Data storage device employing a run-length mapping table and a single address mapping table |
摘要 |
A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. When a write command comprising a logical block address (LBA) is received, a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold, a new run-length mapping entry in a run-length mapping table (RLMT) is created. When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created.
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申请公布号 |
US8443167(B1) |
申请公布日期 |
2013.05.14 |
申请号 |
US20090639794 |
申请日期 |
2009.12.16 |
申请人 |
FALLONE ROBERT M.;BOYLE WILLIAM B.;WESTERN DIGITAL TECHNOLOGIES, INC. |
发明人 |
FALLONE ROBERT M.;BOYLE WILLIAM B. |
分类号 |
G06F12/10 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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