发明名称 |
Probe speculative address file |
摘要 |
An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value. |
申请公布号 |
US8438335(B2) |
申请公布日期 |
2013.05.07 |
申请号 |
US20100892476 |
申请日期 |
2010.09.28 |
申请人 |
STEELY, JR. SIMON C.;HASENPLAUGH WILLIAM C.;INTEL CORPORATION |
发明人 |
STEELY, JR. SIMON C.;HASENPLAUGH WILLIAM C. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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