发明名称 |
SHUFFLE PATTERN GENERATING CIRCUIT, PROCESSOR, SHUFFLE PATTERN GENERATING METHOD, AND INSTRUCTION |
摘要 |
<p>A shift duplicating unit carries out a one-bit left bit shift of individual indexes on the basis of an index line (702) of four (bit width of eight bits) indexes that have been inputted, and outputs an index line (902) obtained by making two-by-two duplicates of each index. An adder then outputs a shuffle pattern (703) obtained by adding the values of 1, 0, 1, 0, 1, 0, 1, 0 in order from the left end to the index line (902).</p> |
申请公布号 |
WO2013057872(A1) |
申请公布日期 |
2013.04.25 |
申请号 |
WO2012JP05819 |
申请日期 |
2012.09.13 |
申请人 |
PANASONIC CORPORATION;UEDA, KYOKO;BABA, DAISUKE |
发明人 |
UEDA, KYOKO;BABA, DAISUKE |
分类号 |
G06F9/315;G06F7/76;G06F9/30 |
主分类号 |
G06F9/315 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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