发明名称 |
FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT |
摘要 |
Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height {surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal- containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device. |
申请公布号 |
WO2013052067(A1) |
申请公布日期 |
2013.04.11 |
申请号 |
WO2011US55422 |
申请日期 |
2011.10.07 |
申请人 |
INTEL CORPORATION;LINDERT, NICK;STEIGERWALD, JOSEPH, M.;SINGH, KANWAL, JIT |
发明人 |
LINDERT, NICK;STEIGERWALD, JOSEPH, M.;SINGH, KANWAL, JIT |
分类号 |
H01L27/108;H01L21/8242 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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