发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT DESIGN DEVICE, METHOD, AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To perform layout design that achieves an optimum wiring efficiency in an analog circuit. <P>SOLUTION: Components constituting a function block are grouped for each type. Arrangement of the components within the function block is determined on the basis of a connection relationship between the components. At this point, the number of divisions for components constituting a group can be taken into consideration. The arrangement order of the function blocks is determined so as to perform arrangement in descending order of area or width. Preferably, the arrangement order can be adjusted by user's specification. The arrangement position of each function block is determined on the basis of the arrangement order and connection information for the entire circuit. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013061901(A) 申请公布日期 2013.04.04
申请号 JP20110201405 申请日期 2011.09.15
申请人 RENESAS ELECTRONICS CORP 发明人 AOKI TOMOKO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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