发明名称 SEMICONDUCTOR DEVICE
摘要 Provided is a method of manufacturing a semiconductor device capable of preventing, in a SOG etch back planarization process in a multi-layered wiring process, degradation in long-term reliability with respect to the entering of moisture caused by a fuse opening portion. A fuse is shaped so that polycrystalline silicon extends to a lower part of a guard ring provided in a first layer of metal for preventing the entering of moisture from the fuse opening portion. Thus, a metal wiring used for connection to an electrode of the fuse and a metal wiring of the guard ring become equal in height, and hence an SOG layer can be prevented from reaching the inside of an IC.
申请公布号 US2013082349(A1) 申请公布日期 2013.04.04
申请号 US201213628137 申请日期 2012.09.27
申请人 HASEGAWA HISASHI 发明人 HASEGAWA HISASHI
分类号 H01L23/525 主分类号 H01L23/525
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