发明名称 Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60GHz Power Amplifier Circuits
摘要 Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
申请公布号 US2013078933(A1) 申请公布日期 2013.03.28
申请号 US201113243986 申请日期 2011.09.23
申请人 SOE ZAW;TENSORCOM, INC. 发明人 SOE ZAW
分类号 H04W88/02;H03B11/00 主分类号 H04W88/02
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