发明名称 Counter circuit and solid-state imaging device
摘要 According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.
申请公布号 US8406370(B2) 申请公布日期 2013.03.26
申请号 US201113179009 申请日期 2011.07.08
申请人 HIZU KAZUKI;KABUSHIKI KAISHA TOSHIBA 发明人 HIZU KAZUKI
分类号 H03K23/00 主分类号 H03K23/00
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