发明名称 |
Low power and low spur sampling PLL |
摘要 |
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
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申请公布号 |
US8395427(B1) |
申请公布日期 |
2013.03.12 |
申请号 |
US20100973323 |
申请日期 |
2010.12.20 |
申请人 |
GAO XIANG;BAHAI AHMAD;BOHSALI MOUNIR;DJABBARI ALI;KLUMPERINK ERIC;NAUTA BRAM;SOCCI GERARD;NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
GAO XIANG;BAHAI AHMAD;BOHSALI MOUNIR;DJABBARI ALI;KLUMPERINK ERIC;NAUTA BRAM;SOCCI GERARD |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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